Without limiting the scope of the invention, its background is described in connection with existing sampling of semiconductor wafers and data storage wafers. Data storage substrates (wafers) are similar in overall appearance to semiconductor wafers but are typically composed of different materials.
A semiconductor substrate on which circuits are formed is usually a thin disk of a crystalline semiconductor material, most typically silicon, and is termed a wafer. A wafer is formed by slicing a grown crystal ingot or boule. After lapping the wafer into a uniform thickness and surface homogeneity, the wafers are polished to a mirror finish and cleaned. The prepared wafers are then ready for integrated circuit fabrication. In a semiconductor fabrication plant or “FAB,” the wafers are transferred through repeated sequential steps of thermal oxidation, photolithography, etching, doping, and repetitions of the same prior to deposition of metal and dielectric layers and further etching. This process of formation of semiconductor circuits requires sophisticated automated movement of wafers through a clean room environment in the FAB as the microelectronics are formed on the wafer surface. A typical modern FAB will include hundreds of pieces of specialized equipment. The amount of processing that the semiconductor wafer undergoes increases with the complexity of the circuit design. Thus, a 300 mm wafer may travel from 8 to 10 miles during processing, while visiting over 200 process tools to undergo hundreds of individual processing steps.
Wafers are transferred through the FAB in a multi-wafer carrier that is referred to as a FOUP, which stands for Front Opening Unified (or Universal) Pod. Similarly, FOUPS are used to transport and store data storage wafers. Both semiconductor wafers and data storage wafers are round planar disks and FOUPs are available that are generally designed to hold the various dimensions of available wafers and disks.
Present state-of-the-art semiconductor manufacturing is performed using 300 mm wafers although the industry is transitioning to 450 mm wafers and larger diameter wafers are contemplated as larger cylindrical crystalline boules are grown.
Ultimately, the circuits on the finished semiconductor wafers are inspected for fundamental elemental characteristics and on-wafer function and performance. As part of this inspection process, the critical dimensions of the wafer are measured, typically by high resolution imaging at sub-nanometer resolution levels. The industry standard method of obtaining the best resolution of the submicroscopic structure of a region of a semiconductor circuit is by scanning electron microscopy (SEM) and/or transmission electron microscopy (TEM). With an SEM, a primary electron beam is focused to a fine spot that scans the surface of the wafer to be observed. Secondary electrons are then emitted from the surface as it is impacted by the primary beam, and these secondary electrons are detected by the SEM to form an image. Using a TEM, a broad beam of electrons is directed at the sample surface, and electrons that are transmitted through the sample are focused to form an image. With TEM imaging, the sample must be sufficiently thin to allow the electrons in the broad beam to travel through the sample and exit on the opposite side. An imaging technique similar to TEM is STEM imaging. In STEM imaging, thin samples are also required but a focused probe is formed at the sample plane. The acronyms (S)TEM or STEM are used to indicate imaging with either STEM or TEM. In addition, other capabilities may be present in certain electron microscopes including Energy Dispersive Spectroscopy (EDS), Energy Dispersive X-ray Spectroscopy (EDX) and Electron Energy-Loss Spectroscopy (EELS). For purposes of these evaluations, (S)TEM samples are cut from the wafers and imaged by (S)TEM as well as other analyses for which the samples are suitable.
Several techniques are known for preparing TEM samples for imaging, including cleaving, chemical polishing, mechanical polishing, broad beam low energy ion milling, or a combination thereof. The disadvantage to these methods is that they are not site-specific and often require that the starting material be sectioned into smaller and smaller pieces, thereby destroying much of the original sample. Other techniques generally referred to as “lift-out” techniques use focused ion beams (“FIB”) to cut the sample from a substrate or bulk sample without destroying or damaging surrounding parts of the substrate. Such techniques are useful in analyzing the results of processes used in the fabrication of the resulting integrated circuits. Techniques where the sample is extracted from the substrate within the FIB system vacuum chamber are commonly referred to as “in-situ” techniques while sample removal outside of the vacuum chamber (as when the entire wafer is transferred to another tool for sample removal) are called “ex-situ” techniques.
A TEM sample is a sample that has been thinned to a sufficient level so as to be electron transparent in a region of interest (ROI) for TEM analysis. The ROI is typically about 2×2 μm in size. The actual TEM sample removed from a semiconductor wafer is typically called a “lamella,” and may have overall dimensions of about 15×8 μm and a thickness of about 15 nm in the ROI. One of the preferred technologies for making a TEM sample at a customer-specified location is to use the focused ion beam (FIB) method set forth above. Typically, a microscope combining both an FIB and an SEM are utilized for creating site-specific TEM lamellae. Such combined FIB-SEM tools are often called “dual beam” lamella production tools.
The resulting lamella samples may then be positioned on a TEM grid that is compatible for use with TEM, SEM or STEM equipment for imaging. There are a large variety of formats of TEM grids, but they are generally designed to be compatible with TEM, SEM or STEM sample holders. Effectively, the sample holders are designed to hold a 3 mm circle or some fraction thereof. As such, there is an industry standard format for TEM grids, which are typically about 3 mm in diameter and about 500 μm thick at the rim. One company that manufactures such grids is Ted Pella, Inc. of Redding, Calif. Generally, there are two types of TEM grids, one where lamella are placed onto the grid and held in place purely by naturally occurring electrostatic forces, and another where lamella are affixed to a region on the grid through an attachment process. Once the lamellae are placed or affixed to the TEM grid, they are then typically manually positioned in the TEM apparatus for imaging.
Whatever methods are used, the preparation of a TEM sample is complex and time consuming. Many of the steps involved in the TEM sample preparation and analysis must be performed using instruments operated manually, which decreases efficiency and increases manufacturing costs. Indeed, some steps require manual movement of the lamellae from one piece of equipment to the next. For example, prepared lamellae samples are typically removed from the TEM sample preparation tool and stored in grid storage boxes, dishes or vials from which individual grids are manually loaded into the TEM imaging tool. The loss of automation at certain stages is a significant detriment to semiconductor chip manufacture. From the foregoing, it appeared to the present inventors that the lamella sample storage and transport system could be greatly improved. Provided herein are innovative workflow control and storage systems and apparatus for preparing, transporting, and imaging samples taken from semiconductor chips.